This invention relates to selective salicidation of source/drain regions of a transistor, for example, for use in the production of electro-static discharge (ESD) transistors connected to circuit input/output pads and used to protect semiconductor devices from damage resulting from electrostatic discharge.
As the size of circuitry within integrated circuits continues to decrease, it is often desirable to include a metal-silicide region as part of the source/drain region. This minimizes the series source/drain resistance and avoids transistor performance degradation. See for example, Silicon Processing for the VLSI Era--Volume 2, Process Integration, pp. 144-152.
However, using metal-silicide regions in source-drain regions of electrostatic discharge (ESD) transistors can be detrimental to circuit performance. ESD can be a source of destruction for semiconductor devices. Various input protection circuits may be used to protect the input circuits from electrostatic discharge damage. However, these same protection circuits are generally not used for output buffers and input/output (I/O) pads due to performance constraints. See for Example, Y. Wei, Y. Lob, C. Wang and C. Hu, MOSFET Drain Engineering for ESD Performance, EOS/ESD Symposium, 1992, pp. 143-148. For output buffers and I/O buffers, n-channel pull-down transistors must be properly designed to ensure adequate ESD performance. These n-channel pull-down transistors used for I/O buffers, n-channel pull-down transistors are sometimes referred to as ESD transistors
However, using metal-silicide regions in source-drain regions of ESD transistors can seriously degrade ESD hardness, increasing the possibility of ESD damage to logic circuitry within semiconductor devices. See for example, C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, ESD Phenomena and Protection Issues in CMOS Output Buffers, IEEE/IRPS, 1987, pp. 174-180. Because of this it is desirable to prevent metal-silicide regions from being included as part of the drain region of an ESD transistor. See, for example, D. Krakauer, K. Mistry, ESD Protection in a 3.3 Volt Sub-Micron Silicided CMOS Technology, EOS/ESD Symposium, 1992, pp. 250-257. It is desirable therefore, to formulate an efficient and effective method which allows selective salicidation of source/drain regions.